Development of the n-XYTER front end board FEB-D for CBM

Employment of highly integrated ASIC front-end electronics in GSI and FAIR detector systems is crucial in view of current and future detector granularity, overall channel number and radiation length to be minimized. Yet, integration of such multi-channel readout chips into detectors brings a severe technological gap up to light, where channel pitch on silicon is found on the order of 50 μm, whereas standard PCB technology realistically allows to create structures at a pitch of 150 μm down to 100 μm in extreme cases. The n-XYTER 128 channel mixed signal chip [1, 2] is used as a prototype detector readout chip for FAIR detector prototyping. It allows to realize a purely data driven readout, which does not rely upon an external trigger. This chip was exemplarily integrated onto a frontend test board (FEB) for the CBM STS project in the past [2]. This work rapidly illuminated the challenges that go about with bridging the technological gap in feature size from silicon to current PCB production capabilities, if an intermediate pitch adapter is to be omitted. With version FEB D, this challenge could be resolved in a cooperative effort between the GSI detector laboratory and the German PCB manufacturer Würth Elektronik.